Low-latency Deterministic Forwarding for Multi-modal Connection Using Time-Sensitive Networking


This poster proposes a low-latency deterministic forwarding technology for multi-modal data based on time-sensitive networks. It presents the design and implementation of an FPGA-based switch that can handle data frames of different protocols, including Ethernet, PROFINET, and EtherCAT. The switch consists of an input port, an output port, a clock module, an exchange module, and a gate control module. Its core is the switch module, which comprises four sub-modules, i.e., protocol identification, caching, handling, and conversion. To prioritize critical traffic over normal traffic, the switch implements a priority-based scheduling algorithm. It also provides timestamping for performance analysis. Through the proposed technology and switch design, the poster aims to improve low-latency deterministic forwarding for time-sensitive multi-modal data.

In Proceedings of the ACM Turing Award Celebration Conference - China 2023
Research Assistant Professor

My research interests include AIoT, edge computing, and mobile security.